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| MC145423 Freescale Semiconductor, Inc. Semiconductor Products Sector MOTOROLA ABSOLUTE MAXIMUM RATINGS (Voltage Referenced to VSS) Rating DC Supply Voltage Voltage, Any Pin to VSS DC Current, Any Pin (Excluding VDD, VSS) Operating Temperature Storage Temperature Symbol VDD - VSS V I TA Tstg Value -0.5 to 6 -0.5 to VDD + 0.5 10 -40 to 85 -85 to 150 Unit V V mA C C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid applications of any voltage higher than maximum rated voltages to this highimpedance circuit. For proper operation, it is recommended that Vin and Vout be constrained to the range VSS (Vin or Vout Pin Selectable Master/Slave ) VDD. Reliability of operation is enhanced C. Limited Distance to an appropriate if unused inputs areN Modem tied I logic level (e.g., , Reither VSS or VDD). Product Preview Universal Digital Loop Transceiver (UDLT-3) Freescale Semiconductor, Inc... O The MC145423 is a CMOS integrated circuit designed CT of the major building blocks in digital subscriber voice/da U telephone RECOMMENDED OPERATING CONDITIONS (TA = -40 to 85C) ND systems and remote data acquisition and contro O UDLT-3 incorporates into one device, all the funct The Parameter Pins Typ Max Unit ICMin M the MC145421 (ISDN UDLT-2 master), MC145425 (ISDN DC Supply Voltage VDD SE 4.5 -- V slave), MC145422 (UDLT-1 5.5 master), and MC145426 (UD E Power Dissipation (PD = VDD) VDD = 5 V VDD -- -- 80 mW slave). AL CVDD Since these modes/functions are pin mW selectable, the MC VDD = 5 V S -- -- 80 Power Dissipation (PD = VSS) E MSI can be used in telephone switch line cards, as well as rem Frame Rate 7.9 8.0 8.1 kHz RE telsets or data terminals. F CCI CLK Frequency (MSI = 8 kHz) CCI MHz * -- DD = 4.52.048 5.5 V V V to BY UDLT-1 (CCI = 256 x MSI) -- D UDLT-2 8.192 *-- 28-Pin SOIC and TSSOP8.29 Packages VE I *-- Protocol Independent Frame Rate Slip* -- 0.25 % CH * Pin Controlled Power-Down Data Clock Rate (Master Mode) TDC-RDC kHz AR * 64 Sensitivity Control in 4100 Mode LI Master UDLT-1 -- *128 2.048 MHz Output in Slave Mode UDLT-2 -- 4100 SDCLK (UDLT-2 Only) Modulation Baud Rate UDLT-1 UDLT-2 LO1, LO2 UDLT-2 Features 16 -- 4100 kHz kHz *-- Synchronous-- Duplex256 kbps Voice and Data Full 160 -- -- 512 Communications in a 2B+2D Format for ISDN Compa * The slave's crystal frequency divided by 512 (UDLT-1) or 1024 (UDLT-2), must equal the master's MSI frequency 0.25% for optimum * Provides CCITT Basic Access Data Transfer Rate (2B+ operation. ISDNs on a Single Twisted Pair Up to 1 km on 26 AW Larger Cable UDLT-1 Features * Pin Controlled Loopback * Automatic Power-Up/Down (Slave) * Full Duplex Synchronous 64 kbps Voice/Data Channel 8 kbps Signaling Data Channels Over One 26 AWG Wi to 2 km This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. 4 For More Information On This Product, TELECOMMUNICATIONS Go to: www.freescale.com (c) Motorola, Inc., 2000. All rights reserved. MC145423 Freescale Semiconductor, Inc. PIN ASSIGNMENT VSS Vref LI LB VD SDI1 SDI2 FRAME 10/20 SDCLK/8kHz SDO1 SDO2 SE/(Mu/A) PD MOD TRI/SQ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD LO1 MASTER/SLAVE LO1 LO2 LO2 Rx RE2/BCLK RE1/CLKOUT LI SENS/2.048 MHz TDC-RDC/XTALout CCI/XTALin MSI/TONE EN1-TE1 CCI/XTALIn (TDC-RDC)/ EN2-TE2/SIE/B1B2 XTALout Tx MODULATOR B1 B2 D1 BLOCK D D2 Freescale Semiconductor, Inc... H RC A D VE I O IC M 28-PIN SOIC/TSSOP PACKAGES SE E AL C MSI/TONE ES E MOD TRI/SQ FR FRAME 10/20 BY MASTER/ SLAVE LI SENS/ 2.048 MHz N ,I R TO C OSC DU N C. REGIST LOGIC CLKOUT BCLK Mu/A SE LATCH SEQUENCE AND CONTROL SE LATCH SE LATCH TDC/RDC VD CONTROL VD D2 REGISTER LOGIC D1 LI DEMODULATOR B2 Vref B1 2 For More Information On This Product, TELECOMMUNICATIONS Go to: www.freescale.com TELECOMMU MC145423 Freescale Semiconductor, Inc. DIGITAL CHARACTERISTICS (VDD = 5 V 10%, TA = - Parameter Input High Level B18 tp4 Input Low Level Input Current (Digital Pins) B17 Input Current LI Input Capacitance Output High Current (Excluding Tx and PD) . Output Current Low (Excluding Tx and PD) IN Freescale Semiconductor, Inc... H RC A B18 ANALOG CHARACTERISTICS (VDD = 5 V 10%, TA = Parameter Modulation Differential Amplitude (RL = 440 ) Modulation Differential Offset Vref Voltage, Typically 9/20 x (VDD - VSS) PCM Tone Level Demodulator Input Amplitude* DON'T CARE tp2 B15 B16 B17 Demodulator Input Impedance (LI to Vref) * The input level into the demodulator to reliably demodulate incoming tp5 B12 B13 B14 th2 VALID D VE I tp3 B11 BY E RE F HIGH IMPEDANCE tw(L) B12 E AL SC tsu5 B13 S CT ULow Current Tx Output D ON IC M PD Output High Current -- Slave Mode* E th1 tw(H) B14 B15 Tx Output HighOR Current , C B16 PD Output Low Current -- Slave Mode* Tx, SDO1, SDO2, and VD Three-State Current XTAL Output High Current XTAL Output Low Current * To overdrive PD from a low level to 3.5 V, or a high level to 1.5 V requ tp1 B11 tsu6 SDO1, SDO2 RE1 TE1 Figure 1. UDLT-1 Slave Timing Nonsynchronous BCLK 8 For More Information On This Product, TELECOMMUNICATIONS Go to: www.freescale.com SDI1, SDI2 VD Rx Tx tdly3 tp6 TELECOMMU MC145423 Freescale Semiconductor, Inc. MASTER SWITCHING CHARACTERISTICS (VDD = 5 V 10%, TA = -40 to 85C, CL = 50 CHARACTERISTICS (VDD = 5 SLAVE SWITCHING pF) Parameter Input Rise Time: All Digital Inputs Input Fall Time: All Digital Inputs Pulse Width: TDC, RDC, RE1, RE2, MSI, SDCLK (UDLT-2) CCI Duty Cycle Propagation Delay: MSI to SDO1, SDO2, VD (PD = VDD) TDC to Tx MSI, TE1, TE2, RE1, RE2 to TDC-RDC Setup Time Figure No. Symbol Min Max Parameter Unit s s F tr 2 Input Rise Time: -- Digital Inputs All tf -- Input Fall Time: All Digital Inputs2 Freescale Semiconductor, Inc... TDC-RDC to MSI, TE1, TE2, RE1, RE2, Hold Time Rx to TDC-RDC Setup Time Rx to TDC-RDC Hold Time SDI1, SDI2 to MSI Setup Time SDI1, SDI2 to MSI Hold Time MSI Rising Edge to First SDCLK Falling Edge (UDLT-2 Only) TE Rising Edge to First Tx Data Bit Valid TE1,TE2 Falling Edge to Tx High IV Impedance TDC-RDC Rising Edge to Tx Data Bits D- 8 Valid 2 C SDCLK Rising Edge to SDO1, SDO2 Bit Valid AR (UDLT-2 Only) SDI1, SDI2 Data Setup (Data Valid Before SDCLK Falling Edge) (UDLT-2 Only) SDI1, SDI2 Data Hold (Data Valid After SDCLK Falling Edge) (UDLT-2 Only) PD, LB Setup (PD, LB Valid Before MSI Rising Edge) PD, LB Hold (PD, LB Valid After MSI Rising Edge) H E BY E RE F E AL SC SE tp ns Clock Output Pulse Width: BCLK 90 -- Crystal Frequency tw2(H,L) 45 55 % Propagation Delay Times: . tPLH, ns C EN1, EN2, TE1 Rising to BCLK (TONE = VDD) tPHL -- IN 50 EN1, EN2, TE1 Rising to BCLK (TONE = VSS) --, 50 BCLK to EN1, EN2, TE1 Falling OR T 20 tsu3 -- ns RE1 Rising to BCLK (UDLT-1) UC 50 RE1 Falling to BCLK (TONE = VDD) (UDLT-1) th5 D -- ns RE1 Falling to BCLK (TONE = VSS) (UDLT-1) N tO 30 -- ns BCLK to Tx ICsu5 TE1,TE2 to SDO1, SDO2 30 -- ns M th1 Rx to BCLK Setup Time tsu2 30 th2 30 Rx to BCLK Hold Time -- -- ns ns ns tSDI1, SDI2 to TE Setup Time 50 -- P1LH SDI1, SDI2 to TE Hold Time tsu6 -- 50 ns EN1, EN2 Rising Edge to DCLK Rising Edge (UDLT-2) tsu7 -- 50 ns EN1, EN2 Rising Edge to First Tx Data Bit Valid tdly -- 70 ns BCLK Rising Edge to Tx Data Bits 2 - 8 Valid tsu8 -- 135 ns DCLK Pulse Width High (UDLT-2) tsu9 50 -- DCLK Pulse Width Low (UDLT-2) ns DCLK Rising Edge to SDO1, SDO2 (UDLT-2) th3 20 -- ns SDI1, SDI2 Setup (SDI1, SDI2 Valid Before DCLK Falling Edge) (UDLT-2) tsu10 50 -- ns SDI1, SDI2 Hold (SDI1, SDI2 Valid After DCLK th4 20 -- ns Falling Edge) (UDLT-2) EN1, TE1 Rising Edge to VD Valid SE PIN TIMING Parameter LB, PD Hold (LB, PD Valid After SE Falling Edge) SDO1, SDO2, VD High Impedance After SE Falling Edge SDO1, SDO2, VD Valid After SE Rising Edge LB, PD Setup (LB, PD Valid Before SE Rising Edge) F 6 For More Information On This Product, TELECOMMUNICATIONS Go to: www.freescale.com TELECOMMU Freescale Semiconductor, Inc... MC145423 12 tw2 tp MSI th5 TDC/RDC th5 th5 tw2 tsu3 th5 H RC A D VE I TE1/TE2 tsu6 tsu7 B17 B18 tdly BY Tx B11 B12 B13 B14 B15 B16 E RE F tp RE1/ RE2 th1 tsu5 B11 tP1LH B12 B13 B14 E AL SC Rx B15 B16 B17 B18 S tw2 O IC EM SDCLK tsu8 B1 tsu9 th3 B1 DON'T CARE Figure 5. UDLT-2 Master Timing B2 tdly3 /tPHL PLH tw2 Freescale Semiconductor, Inc. For More Information On This Product, TELECOMMUNICATIONS Go to: www.freescale.com B2 VALID tw(H) tp5 tp2 DON'T CARE tw(L) tp3 B13 B14 B15 B16 B17 B18 HIGH IMPEDANCE , OR T UC ND SDO1, SDO2 SDI1, SDI2 DON'T CARE DON'T CARE C IN tPLH/tPHL . VD BCLK tsu10 th4 PD/LB VALID B1 tp1 TE1 tp4 RE1 Figure 2. UDLT-1 Slave TELECOMMU Tx B11 B12 Freescale Semiconductor, Inc... MC145423 10 tw(H) H RC A BCLK tp5 tw(L) tp2 tp1 D VE I EN1 BY tp1 EN2 E RE F tsu7 B23 B24 tdly1 B12 B22 tsu5 B12 B18 B22 th1 B13 B14 B15 B16 B17 B21 B13 B14 B15 B16 B17 B18 B21 Tx B11 B25 B26 B27 B2 B18 B11 E AL SC Rx B11 B23 B24 B25 B26 B27 B28 B11 S tPHL tw(H) tw(L) SDCLK tdly2 B1 tsu9 B1 th3 tp VALID tsu3 tsu3 O IC EM Figure 3. UDLT-2 Slave Timing B2 Freescale Semiconductor, Inc. For More Information On This Product, TELECOMMUNICATIONS Go to: www.freescale.com B2 tw2 th5 th5 tw2 tPLH/tPHL B11 B12 B13 B14 tp B15 B16 B17 B18 SDO1, SDO2 SDI1, SDI2 , OR T UC ND tdly3 C IN VD MSI . CCI, TDC/ RDC tsu3 th5 TE1 Tx HIGH IMPEDANCE Figure 4. UDLT-1 TELECOMMU RE1 MC145423 Freescale Semiconductor, Inc. MC145423 UDLT-3 PIN STATES FOR UDLT-1 SLAVE MODE (continued) MC145423 Pin No. 23 24 25 26 Pin Name RE2/ BCLK Rx LO2 LO1 MASTER/ SLAVE VDD In/out Output Input Output Output Input Power UDLT-1 Slave Mode Powered-Up Normal BCLK = 128 kHz 64 kbps Data In Modulator Out Modulator Out 1 +V LB Low BCLK = 0 Don't Care Modulator Out Modulator Out 1 +V UDLT-1 Slave Mode Powered-Down SE TONE = 0, Off No Valid Burst Rec'd BCLK = 128 kHz Don't Care LO2 = LO1 LO1 = LO2 Valid Burst Rec'd BCLK = 128 kHz TONE = 1, On No Valid Burst Rec'd LB, PD Valid Burst Rec'd BCLK = 128 kHz Don't Care LO2 = LO1 th PREVIO INTERNAL BCLK = 128 kHz Don't Care SDO1, SDO2, VD Don't Care . Freescale Semiconductor, Inc... 27 28 MC145423 UDLT-3 PIN STATES FOR UDLT-1 MASTER MODE EE MC145423 Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin Name VSS Vref LI LB VD SDI1 SDI2 FRAME 10/20 SDCLK SDO1 SDO2 SE/(Mu/A) PD MOD TRI/SQ Tx EN2-TE2/ SIE/B1B2 D VE Normal In/out I H Power Power Supply RC A Gnd Analog Ref Input Input Output Input Input Input AGND VDD/2 Analog In 1 Digital out 8 kbps Data In 8 kbps Data In 0 BY FRUDLT-1 Master Mode Powered-Up LB Low Power Supply Gnd AGND VDD/2 Don't Care 0 Digital out 8 kbps Data In 8 kbps Data In 0 E AL SC S+V O IC EM 1 R TO LO1UC = LO2 LO1 = LO2 D N LO2 = LO1 1 +V 1 +V LO2 , = LO1 IN C tdly1 Figure LO1 = LO2 1 +V 6. SE UDLT-1 Master Mode Powered-Down SE Low Power Supply Gnd AGND VDD/2 Analog In State Latched Normal Power Supply Gnd AGND VDD/2 Analog In Don't Care Digital out 8 kbps Data In 8 kbps Data In 0 SE Low Power Supply Gnd AGND VDD/2 Analog In Don't Care High Impedance State Latched State Latched 0 High Impedance State Latched State Latched 0 Don't Care High Impedance High Impedance High Impedance High Impedance High Impedance Output Output Input Input Input Output Input 8 kbps Data Out 8 kbps Data Out High Impedance 8 kbps Data Out High Impedance 8 kbps Data Out 8 kbps Data Out High Impedance 8 kbps Data Out High Impedance 1 1 0 64 kbps Data Out SIE Digital In 1 1 0 64 kbps Data Out SIE Digital In 0 State Latched 0 64 kbps Data Out SIE Digital In 1 0 0 64 kbps Data Out SIE Digital In 0 State Latched 0 64 kbps Data Out SIE Digital In 16 For More Information On This Product, TELECOMMUNICATIONS Go to: www.freescale.com TELECOMMU MC145423 Freescale Semiconductor, Inc. SOIC PACKAGE PINOUT COMPARISON MC145423 UDLT-3 PIN STATES FOR UDLT-1 SLAV UDLT-1 Slave Mode MC145423 Powered-Up UDLT-2 Master UDLT-2 Slave Pin Pin MC145421 MC145425 No. Name In/out Normal LB Low Pin Pin Pin Pin 1 VSS Power Power Supply Power Supply No. Name No. Name Gnd Gnd 1 VSS 1 VSS 2 Vref Analog AGND AGND . 2 Vref Vref Ref VDD/2 VDD/2 NC2 I 33 LI LI LI Analog In LB 1 VD Digital Out DI1 8 kbps Data In DI2 8 kbps Logic 1 Data In DCLK 0 D1O D2O SDCLK/8kHz (Mu/A) 8 kbps PD Data Out Logic 1 8 kbps DataTx Out 1=EN2 Mu, 0=A EN1 1 TONE 0 (XTALin) CCI 64 kbps (XTALout) XTL Data Out 1/0 B1B2 2.048 MHz Out EN1 = 8 kHz CLKOUT 1/0 TONE BCLK Rx XTALin LO2 4.096 MHz LO1 XTALout 4.096 MHz Logic 1 2.048 MHz VDD RE1 = 8 kHz Analog In 0 Digital Out 8 kbps Data In 8 kbps Data In 0 SDCLK/8kHz 8 kbps Data Out 8 kbps Data Out 1= Mu, 0=A 1 0 64 kbps Data Out 1/0 B1B2 EN1 = 8 kHz 1/0 TONE XTALin 4.096 MHz XTALout 4.096 MHz 2.048 MHz RE1 = 8 kHz UDLT-3 PINOUT VERSUS MC145421DW/22DW/25DW/26DW (UDLT-1/UDLT-2 MASTER/SLAVE) PINOUT UDLT-3 MC145423 Pin No. 1 2 3 4 Pin Name VSS Vref LI LB VD SDI1 SDI2 FRAME 10/20 SDCLK/8kHz SDO1 SDO2 SE/(Mu/A) PD MOD TRI/SQ Tx EN2-TE2/SIE/ B1B2 EN1-TE1 MSI/TONE CCI/XTALin TDC-RDC/ XTALout LI SENS/ 2.048 MHz RE1/CLKOUT RE2/BCLK Rx LO2 LO1 MASTER/ SLAVE VDD 24 20 8 10 11 12 UDLT-1 Master MC145422 Pin No. 1 2 3 5 6 7 9 Pin Name VSS Vref LI LB VD SI1 SI2 Logic 0 High Impedance SO1 SO2 SE D VE PD I UDLT-1 Slave MC145426 Pin No. 1 2 3 5 6 7 9 Pin Name VSS Vref LI LB VD SI1 Logic E L0 CA S SDCLK SI2 Freescale Semiconductor, Inc... 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 S , OR Input3 T 44 LB 4 Input LB UC 55 D VD VD 5 Output ON SDI1 D1I 6 Input IC 66 M7 D2I 7 E 7 8 8 9 10 9 11 10 12 11 13 14 12 15 13 16 14 17 15 18 16 17 19 18 20 21 19 22 23 20 21 SDI2 Logic 1 DCLK FRAME D1O 10/20 D2O SDCLK/ 8kHz SE SDO1 PD Logic 1 SDO2 Tx TE2 SE/(Mu/A) TE1 PD Input 8 Input 9 BY E 8 RE F 10 11 12 SO1 SO2 Mu/A PD Logic 0 10 Output 11 Output 12 Output 13 14 Input I/O15 H RC Logic 0 A 16 14 15 13 17 18 Tx 15 Tx B1B2 Logic 0 SIE TE1 MSI CCI TDC/RDC Logic 0 LI SENS RE1 20 18 19 22 23 14 13 16 17 TE1 (Tone) TE (XTALin) X1 (XTALout) X2 2.048 MHz Out RE1 (BCLK) CLK Rx LO2 LO1 Logic 1 MSI 16 MOD Input TRI/SQ CCI 17 Tx Output TDC/RDC 18 EN2-TE2/ Logic 0 SIE/B1B2 LI SENS EN1-TE1 RE1 MSI/ RE2 TONE Rx CCI/ LO2 XTALin LO1 TDC-RDC/ XTALout Logic 0 LI SENS/ 2.048 MHz VDD RE1/ CLKOUT Input Output 19 Input 20 21 Input 22 23 Output Output 24 Output High Impedance 19 22 23 Rx LO2 LO1 Logic 0 VDD 24 VDD 24 22 14 For More Information On This Product, TELECOMMUNICATIONS Go to: www.freescale.com TELECOMMU MC145423 Freescale Semiconductor, Inc. PIN DESCRIPTIONS VSS Negative Supply (Pin 1) This is the most negative power pin, and should be tied to system ground (0 V). Vref Voltage Reference Output (Pin 2) This is the output from the internal reference supply (mid-supply) and should be bypassed to both VSS and VDD with 0.1 F capacitors. This pin usually serves as an analog ground reference for transformer coupling of the device's incoming bursts from the line. No external load should be placed on this pin. LI Line Input (Pin 3) synchronization and the absence of detected bitFOR UDLT-1 MAS MC145423 UDLT-3 PIN STATES errors. VD is a CMOS output and is high impedance when SE UDLT-1 Ma is low. MC145423 Power Master Mode: VD changes state on the rising Pin Pin edge of MSI, when PD is high. When PD is low, VD No. Name In/out Normal LB L changes state at the end of demodulation of a 17 EN1-TE1 Input TE1 8 transmission burst and does not change again TE1 8 kHz until 18 MSI/TONE Input MSI 8 it MSI 8 three MSI rising edges have occurred, at which timekHz goes low, or19 until the next demodulation of CCI 2.048 MHz CCI 2.04 a burst. CCI/ Input . Slave Mode: If no transmissions from the master XTALin C have been receivedTDC-RDC/ Ilast 250 s, as TDC-RDC within the N Input 20 TDC, determined by an internal R oscillator, VD will go low. XTALout Data Clk Data O 21 Input Digital In SDI1 and SDI2 ULI SENS/ D 2.048 MHz LI Sensitivity D Channel Signaling Data Bit Inputs 1 and 2 ON RE1/ Input RE1 8 kHz C 22 (Pins 6Iand 7) CT Freescale Semiconductor, Inc... Digit LI Sen This pin is the input to the demodulator for the E incoming bursts. This input has an internal 240 E R k F resistor tied to the Vref pin, so an external capacitor or Y line transformer may be used to couple B input signal the to the device with no dc offset. ED Master Mode (UDLT-1): These inputs Highthe are Impedance S 23 RE2/ Don't Care 8 LE kbps serial data inputs in UDLT-1 mode. Data on BCLK loaded on the rising edge of MSI for CA these pins is24 S Rx Input 64 kbps Data In EM RE1 8 CLKOUT High Imp 64 kbps V HI C LB AR 4) Loopback Low Input (Pin Master Mode: A low on this pin ties the internal modulator output to the internal demodulator input, which loops the entire burst for testing purposes. During the loopback operation, the LI input is ignored, and the LO1 and LO2 outputs are driven to equal voltages. The state of the LB pin is internally latched if the SE pin is held low. This feature is only active when the PD input is high. Slave Mode: When this pin is low and PD is high, the incoming B channels from the master are burst back to the master, instead of the Rx B channel input data. The SDI1 and SDI2 functions operate normally in this mode, and the BCLK (pin 23) is held low. Additionally, for both the UDLT-1 and UDLT-2 mode, when the TONE (pin 18) and loopback functions are active simultaneously, the loopback function overrides the TONE function. VD Valid Data Output (Pin 5) A high level on this pin indicates that a valid line transmission has been demodulated. A valid line transmission burst is determined by proper transmission to the slave. The state of these pins is 25 LO2 Output Modulator Out LO2 = latched if SE is held low. Slave Mode (UDLT-1): These inputs are the 26 LO1 Output Modulator Out LO1 = 8 kbps serial data inputs in UDLT-1 mode. Data on 27 MASTER/ Input 0 0 these pins is loaded on the rising edge of TE1 for SLAVE transmission to the master. If no transmissions from 28 VDD Power +V +V the master are being received and PD is high, data on these pins will be loaded into the part on an internal signal. Therefore, dataUDLT-3 PIN STATES FOR UDLT-2 SLAV MC145423 on these pins should be steady until synchronous communication with the master has been established, as indicated by the high on VD. Master Mode (UDLT-2): These inputsUDLT-2 Slave Mode are the Powered-Up 16 kbps serial data MC145423UDLT-2 mode. Two bits inputs in Pin Pin should be clocked into each of these inputs between No. of the MSI frame reference clock. The LB Low Name In/out Normal the rising edges 1 VSS Power Power first bit of each D channel is clocked into an Supply Power Supply Gnd intermediate buffer on the first falling edge Gnd of the SDCLK following the rising edge of MSI. AGND The second AGND 2 Vref Analog Ref VDD VDD/2 bit of each D channel is clocked in on the next /2 negative transition ofLI SDCLK. If further SDCLK Analog In the 3 Input Analog In negative edges occur, new information is serially Input 1 0 4 LB clocked into the buffer replacing the previous data, 5 VD Output Digital Out one bit at a time. Buffered D channel bits are burst to Digital Out the slave on 6 next rising edge of the MSI frame the SDI1 Input 16 kbps 16 kbps Data In reference clock. The state of these pins is latched if SE Data In is held low. 7 SDI2 Input 16 kbps 16 kbps Data In Slave Mode (UDLT-2): These inputs Data In are the 16 kbps serial dataFRAME in UDLT-2 mode. The D inputs 8 Input 1 1 channel data bits are clocked in serially on the 10/20 negative edge of the 16 kbps SDCLK output kHz pin. 9 SDCLK Output 16 16 kHz 20 For More Information On This Product, TELECOMMUNICATIONS Go to: www.freescale.com TELECOMMU MC145423 Freescale Semiconductor, Inc. MC145423 UDLT-3 PIN STATES FOR UDLT-2 SLAVE MODE (continued) UDLT-3 PIN STATES FOR UDLT-2 MAS MC145423 UDLT-2 Slave Mode Powered-Up In/out Output Output Input I/O Input Output Output Output Input Normal 16 kbps Data Out 16 kbps Data Out 1/0 Mu/A 1 1 128 kbps Data Out* EN2 8 kHz EN1 8 kHzY LB Low 16 kbps Data Out 16 kbps Data Out 1/0 Mu/A 1 1 128 kbps Data Out* MC145423 Pin No. 10 11 12 Pin Name SDO1 SDO2 SE/ (Mu/A) PD MOD TRI/SQ Tx EN2-TE2/ SIE/B1B2 EN1-TE1 MSI/ TONE CCI/ XTALin TDC-RDC/ XTALout LI SENS/ 2.048 MHz RE1/ CLKOUT RE2/ BCLK Rx LO2 LO1 MASTER/ SLAVE VDD UDLT-2 Slave Mode MC145423 UDLT-2 Maste Powered-Down Pin Pin TONE = 0, Off Name TONE No. In/out = 1, On Normal LB L No Valid Burst Rec'd Data Not Changed Data Not Changed 1/0 Mu/A 1 ValidVSS Burst Rec'd No Valid Power Burst Rec'd Valid Power Supply Burst Rec'd Gnd 16 kbpsVDD/2 AGND Data Out Analog In 16 kbps 1 Data Out Digital Out 1/0 16 kbps Data In Mu/A 16 kbps Data In 0 11 50016 kHz Hz Tone Out Data 16 kbps Out EN2 8 kHz 16 kbps Data Out EN1 8 kHz 1 1 Tone 1 XTAL1 8.192 MHz 128 kbps* XTAL Out Data 8.192 MHz TE2 8 kHz 2.048 MHz TE1 8 kHz RE1 8 kHz 8 kHz CCI BCLK MHz 4.096 128 kHz TDC-RDC 128Data Clk kbps Data In Digital In LO2Sensitivity = LO1 RE1 8 kHz LO1 = LO2 Power Gn AGND Don't Freescale Semiconductor, Inc... 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Input CH XTAL AR 8.192 MHz Output Output Output Output Input Output Output Input Power XTAL 8.192 MHz 2.048 MHz RE1 8 kHz BCLK 128 kHz 128 kbps Data In Modulator Out Modulator Out 1 +V E IV 1/0 Tone D B S High LE Impedance CA EN2 = 0 EN2 8 S kHz E RE FEN1 8 kHz EN1 = 0 1/0 Tone XTAL 8.192 MHz XTAL 8.192 MHz 2.048 MHz RE1 8 kHz BCLK = 0 Don't Care Modulator Out Modulator Out 1 +V 0 No Tone XTAL 8.192 MHz XTAL 8.192 MHz 2.048 MHz RE1 0 BCLK 128 kHz Don't Care LO2 = LO1 LO2 = LO1 1 +V U 7 D 0 SDI2 0 N O 1 1 IC 8 FRAME 10/ 20 M E 9 64 kbps SDCLK Data Out 10 SDO1 EN2 = 0 11 SDO2 EN1 = 0 PD Data Not Ref 2 16 kbps ref V Analog Data Out Changed 3 LI Input 16 kbps Data Not C. 4 LB Data Out IN Input , Changed 5 VD R Output 1/0 1/0 TO 6 Mu/ASDI1 Input Mu/A C 0 Input 1 Input 0 Digita 16 kbps 16 kbps 1 Input 500 Hz ToneOutput Out EN2 8 kHz 16 k 16 kbp Ou Output EN1 8 kHz Input 16 kbp Ou 120 NoSE/(Mu/A) 1 No Tone Input Tone 13 14 XTAL TRI/SQ XTAL MOD Input 8.192 MHz 8.192 MHz 15 Tx Output XTAL XTAL 8.192 MHz 8.192 MHz 16 EN2-TE2/ Input 2.048SIE/B1B2 2.048 MHz MHz 17 EN1-TE1 Input RE1 0 RE1 8 kHz 18 MSI/TONE Input 19 CCI/XTALin Input BCLK BCLK 128 kHz 128 kHz Input 20 TDC-RDC/ Don't Care XTALout 128 kbps Data In 21 LI SENS/ Input LO2 = LO1 MHzLO2 = LO1 2.048 22 RE1/ Input LO2 =CLKOUT LO1 = LO2 LO1 23 24 25 26 27 28 RE2/BCLK 1 Rx +V LO2 LO1 MASTER/ SLAVE VDD Input 1 Input 1 1 1 128 k Data TE2 8 TE1 8 8k CC 4.096 TDCData Digit Sens RE1 8 RE2 8 kHz RE2 8 1 128 kbps Data In 128 kbps Modulator Out +V Modulator Out 0 +V * Tx is high impedance when TE1 and TE2 are both low, simultaneously. Tx is undefined when TE1 and TE2 are both high, simultaneously. Output +V Output Input Power LO2 = LO1 = 0 +V * Tx is high impedance when TE1 and TE2 are both low, simultaneous Tx is undefined when TE1 and TE2 are both high, simultaneously. 18 For More Information On This Product, TELECOMMUNICATIONS Go to: www.freescale.com TELECOMMU MC145423 Freescale Semiconductor, Inc. which is simultaneous with the transfer of the transmit FRAME 10/20 word. See(Pinpin descriptions for EN2-TE2/SIE/ the 8) B1B2 and EN1-TE2 for more information. The UDLT series of transceivers are designed to Master Mode (UDLT-2): B channel data is input operate using a ping-pong transmission scheme with on this pin and controlled by the RE1, RE2, and TDCan 8 kHz burst rate. Each frame the master device RDC pins. "pings" a burst of data to the slave, which responds Slave Mode (UDLT-2): This pin is an input for with a "pong" burst of data. This pin selects whether the B channel data. B channel 1 data is clocked in on this 8 kHz frame will have a 10-bit data burst for the first eight falling edges of the BCLK output UDLT-1 compatibility or . 20-bit data burst for a following the rising edge of the EN1 output. B channel C UDLT-2 compatibility. RE2/BCLK I eight falling edges of 2 data is clocked in on the nextN A logic low (0 V) selects the UDLT-1 (MC145422/ Receive Data Enable Input 2 or B Channel R, edge of the EN2 the BCLK following the rising MC145426)TO This sets the device to operate with mode. Data Clock Output (Pin 23) output. C one 64 kbps voice/data channel and two 8 kbps U Master Mode (UDLT-1): This pin is high signaling channels. A logic high (VDD) on this pin ND LO2 O impedance. selects the (Pin 25) Line Drive OutputUDLT-2 (MC145421/MC145425) mode. IC Master Mode (RE2 UDLT-2): See pin M This sets the device to operate with two 64 kbps The channels and two LO1 (pin 26) form a pushdescription for RE1 (pin 22). SE LO2 pin, along with16 kbps channels (2B+2D). E output, to drive the twisted pair transmission line. Slave Mode (BCLK UDLT-1 and UDLT-2): pull AL The UDLT-1 drives the twisted pair with a 10-bit, This output provides the data clock for the telset SDCLK C ES 256 kHz modified DPSK (MDPSK) burst, or a square (Pin 9) codec-filter. This clock signal is 128 kHz and begins D Channel Signaling Data Clock Input E Ra burst wave (set by pin 14 MOD TRI/SQ) burst, each 125 s. operating upon the successful demodulationF of Master Mode (UDLT-2): This is the transmit and Y The UDLT-2 drives the twisted pair with a 20-bit from the master. At this time, EN1-TE1 goes high and B receive data clock input for both D channels. See 512 kHz modulated burst. When these pins are idle BCLK starts toggling. BCLK remains active for D SDO1 and SDO2 pin descriptions for more VE and set for square wave modulation, they rest at the 16 periods, at the end of whichItime it remains low information. positive power supply voltage. When these pins are until another burst is received from the master. In this CH Master Mode (UDLT-1): High impedance. idle and set for MDPSK, they rest at Vref. For power manner, synchronizationR A between the master and slave Slave Mode (UDLT-2): This is the transmit and supply voltages less than 4.5 V, squarewave is established and any clock slippage is absorbed each receive data clock output for both D channels. It starts modulation must be used. frame. If TONE (pin 18) is brought high, then EN1on demodulation of a burst from the master device. TE1/RE1 are generated from an internal oscillator This signal is rising-edge aligned with the EN1 and LO1 until TONE is brought low, or an incoming burst from BCLK signals. After the Line Driver Output (Pin 26) demodulation of a burst, the the master is received. BCLK is disabled when LB is SDCLK line completes two cycles and then remains held low. See thelow until the next burst from the master is pin description for LO2 (pin 25). demodulated. In this manner, synchronization with the Rx MASTER/SLAVE master is established and any clock slip between Receive Data Input (Pin 24) Master/Slave Mode (Pin 27) master and slave is absorbed each frame. Master Mode (UDLT-1): The 8-bit B channel A logic low (0 V) on this pin selects master and a 8 kHz Slave Mode (UDLT-1): This pin outputs data is clocked into the device on this pin, on the logic high (VDD) selects slave. equivalent to TE1. falling edges of TDC-RDC, under the control of RE1. VDD Slave Mode (UDLT-1): The 8-bit B channel data SDO1 and SDO2 PositiveD Channel Signaling Data Outputs 1 and 2 Supply (Pin 28) from the telset PCM codec-filter is input on this pin on the eight falling edges of BCLK after RE1 goes high, (Pins 10 and 11) This is the most positive power supply pin. when EN2-TE2/SIE/B1B2, pin 16 is low. When EN2Acceptable operatingMode (UDLT-2): These to 5.5 V. Master voltages are from 4.5 V serial outputs TE2/SIE/B1B2, pin16 is high, the receive data word is provide the 16 kbps D channel signaling information latched in during the high period of EN1-TE1, pin 17 from the incoming burst. Two data bits should be clocked out of each of these two outputs between the rising edges of the MSI frame reference clock. The rising edge of MSI produces the first bit of each D channel on its respective pin. Circuitry then searches for a negative D channel clock edge. This data buffer with data from the Rx pin on the next eight falling edges of the TDC-RDC clock. The RE1 and RE2 enables should be roughly leading edge aligned with the TDC-RDC data clock. These enables are rising edge sensitive and need not be high for the entire B channel input period. Slave Mode (CLKOUT UDLT-2): This pin serves as a buffered output of the crystal frequency divided by two. Freescale Semiconductor, Inc... 24 For More Information On This Product, TELECOMMUNICATIONS Go to: www.freescale.com TELECOMMU MC145423 Freescale Semiconductor, Inc. of the incomingalso updatedRx pin will beedge of the EN1 pin is word at the on the rising transmitted to the slave. The PCM word to the slave will have LSB signal. forced low in this mode. In this manner, signal bit 2 to/ MSI/TONE from the slave UDLT is inserted into the PCM words Master Sync Input or the backplane, for the master sends and receives fromTone Enable Input (Pin 18) routing through the PABX for simultaneous voice/data communication. The Mode (MSI): This pin is the master 8 kHz Master state of this pin is internally latched if frame reference input. and held low. of MSI loads the SE pin is brought The rising edge Slave B and D channel data, this mode, this pin is during the Mode (UDLT-1): In which had been input . an input and selects the timeslot used for transferringof the previous frame, into the modulator section NC is low, burst onto the MOD TRI/SQ the receive data word.initiates I pin device, and When this outbound the device the Modulation Select (Pin 14) R, uses the RE1 pin pair cable. same as the MC145426 also the twisted timingO The rising edge of MSI T UDLT-1 slave. When buffering of logic 1, the receive data A logic low (0 V) on this pin selects the MDPSK initiates the this pin is a the B and D channel UC duringTE1 previous frame. MSI should word is latched D during the the timeslot, in modulation which has a slew controlled voltage output demodulated N simultaneously with the transmit word transfer. The the TDCfor reduced EMI/RFI. This output looks like a triangle be approximately leading edge CO is not affected by this aligned with RE1 pinItimingdata clock input signal.selection. waveform that is modulated with different angles for RDC EM Slave Mode (TONE): A high on mode, Master Mode (EN2-TE2 UDLT-2): In thisthis pin causes a the peaks. A logic high (VDD) on this pin, selects S this square wave output for maximum power to the line. 500 Hz as EN2-TE2. This pin, to be with LE pin functions square wave PCM tone along inserted in place A TE1 pin-17 control the outputdata. This feature allows the of the demodulated of data for their SC Tx respective B-channel provideTx output pin. When both keyboard E designer to on the audio feedback for telset Transmit Data Output (Pin 15) TE1 and TE2 are low, the Tx pin is high impedance. RE depressions. F The rising edge of the respective enable produces the Y Master Mode (UDLT-1): This pinB high is first bit ofCCI/XTALinB-channel data on the Tx pin. the selected impedance when TE1 is low. When D is high, this TE1 E Convert Clock Input or Crystal Input (Pin 19) Internal circuitry then scans for the next negative V pin presents new 8-bit B channel data on rising edges HI transition of the TDC-RDC clock. Following this C Master Mode (CCI UDLT-1): A 2.048 MHz of TDC-RDC. event, the next seven bits of the selected B-channel AR B channel data is output Slave Mode (UDLT-1): clock signal should be applied to this pin. This signal data are output on the next seven rising edges of the on this pin on the rising edge of BCLK, while TE1 is is used for internal sequencing and control. This signal TDC-RDC data clock. When TE1 and TE2 are high high. This pin is high impedance when TE1 is low. should be frequency and phase coherent with MSI for simultaneously, data on the Tx pin is undefined. TE1 Master Mode (UDLT-2): This pin is high optimum performance. and TE2 should be approximately leading-edge Slave Mode (XTALin UDLT-1): A 4.096 MHz impedance when both TE1 and TE2 are low. This pin aligned with the TDC-RDC data clock. To keep the Tx serves as an output for B channel information received crystal is tied between this pin and XTALout (pin 20). pin out of the high impedance state, these enable lines from the slave device. The B channel data is under A 10 M resistor across this pin and XTAL and should be high while the respective B channel data is out control of TE1 and TE2 and TDC-RDC. 25 pF capacitors from this pin and XTALout to VSS being output. Slave Mode (UDLT-2): This pin is an output for are required for stability and to ensure start-up. This Slave Mode (EN2-TE2 UDLT-2): Functioning as the B channel data received from the master. pin may be driven from an external source. XTALout EN2-TE2, this pin is an output and serves as an 8 kHz B channel 1 data is output on the first eight cycles of should be left open if an external signal is used on this enable signal for the input and output of the B channel the BCLK output when EN1 is high. B channel 2 data input. 2 data. While EN2 is high, B channel 2 data is clocked Master Mode (CCI UDLT-2): An 8.192 MHz is output on the next eight cycles of the BCLK, when out on the Tx pin on the eight rising edges of the clock should be supplied to this input. The 8.192 MHz EN2 is high. B channel data bits are clocked out on the BCLK. During this same time, B channel 2 input data input should be 50% duty cycle. This signal may free rising edge of the BCLK output pin. is clocked in on the Rx pin, on the eight falling edges run with respect to all other clocks without of the BCLK. EN2-TE2/SIE/B1B2 performance degradation. B Channel 2 Enable Output or EN1-TE1 Slave Mode (XTALin UDLT-2): Normally, an Signal Insert Enable (Pin 16) 8.192 MHz crystal is tied between B Channel 1 Enable Output (Pin 17) this pin and the XTALout (pin 20). A 10 M resistor between Master Mode (SIE UDLT-1): In this mode, this This pin is the logical inverse of EN2-TE2, and XTALin and XTALout and 25 pF capacitors from pin functions as SIE. When held high, this pin causes serves to control Band XTAL data. See the above pin to ensure XTALin channel 1 out to VSS are required signal bit 2, as received from the slave, to be inserted description for more information. EN1 serves as the driven with stability and start-up. XTALin may also be into the LSB of the outgoing PCM word at the Tx pin. slave device's 8 kHz 8.192 MHz signal if a crystal is not an external frame reference signal. The VD The SDI2 pin will be ignored, and in its place, the LSB 250 s have elapsed without a burst from the master being successfully demodulated. This allows the slave device to self power-up and power-down in demand powered loop systems. When held low, the device powers down and the only active circuitry, is that which is necessary for the demodulation of data. When held high, the device is powered up and transmits normally in response to received bursts from the master. Freescale Semiconductor, Inc... 22 For More Information On This Product, TELECOMMUNICATIONS Go to: www.freescale.com TELECOMMU MC145423 Freescale Semiconductor, Inc. DT SUFFIX TSSOP PACKAGE CASE 1168-01 D 28 15 TIP B C A A b1 c c1 N=4 (b) . NC A-A I SECTION 4.7 k 4.7 k 110 5V 5V MASTER/SLAVE LO1 LO2 MOD TRI/SQ SDCLK VSS MC145423 UDLT-3 SLAVE MODE VD EN2-TE2 (I/O)/SIE MCLK VAG VAG-REF 0.01 F SDO1 SDO2 SDI2 MC145484 FST BCLKT BCLKR 0.1 F 1 k 75 k PO+ TG 5V 1 k 68 F TI- TI+ REC PO- 110 SE/(Mu/A) SDI1 N=2 E/2 E E1 1 14 2X Freescale Semiconductor, Inc... PIN 1 INDEX 0.2 A B C e/2 26X e 2X 14 TIPS VIEW A END VIEW TOP VIEW 0.05 0.2 A A 28X b H RC SIDE VIEW A 0.1 M A D VE B IC SEATING PLANE ( 1) GAGE PLANE A1 A2 A 0.25 L VIEW A DIM A A1 A2 b b1 c c1 D e E E1 L 1 MILLIMETERS MIN MAX --1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.19 0.25 0.09 0.20 0.09 0.16 9.60 9.80 0.65 BSC 6.40 BSC 4.30 4.50 0.50 0.70 0 8 14 REF FSR DR Tx EN1-TE1 (I/O) 28 For More Information On This Product, TELECOMMUNICATIONS Go to: www.freescale.com 5V Mu/A VDD PD RO- PI DT Rx RE1/CLKout RE2/BCLK TELECOMMU MSI/TONE 2.048 MHz CCI/XTAL BY BASIC DIGITAL TELSET (D) E 28X RE F E AL SC S VDD 4. 5. LB LI Vref PD O IC EM , OR T NOTES: UC 1. DIMENSIONS AND TOLERANCING PER ASME ND Y14.5M, 1994. 2. 3. DIMENSIONS IN MILLIMETERS. DIMENSION D DOES NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTRUSION IS 0.15 PER SIDE. DIMENSION E1 DOES NOT INCLUDE INTERLEAD FLASH OR MOLD PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 PER SIDE. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSIONS. DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.38. 5V N = 0.5 N = 0.5 MC145423 Freescale Semiconductor, Inc. MULTICHANNEL DIGITAL LINE CARD POWER SUPPLY PACKAGE D DW SU SOIC PA CASE 7 VDD LO1 Vref LO2 LI SDI1 SDI2 SDO1 MSI/TONE Tx Rx TDC/RDC/XTALout CCI/XTALin E UDLT-3 PD MASTER RE1/CLKOUT MODE EN1-TE1 (I/O) A D 8 kHz FRAME SYNC 28 Freescale Semiconductor, Inc... SDO2 SDCLK RE2/BCLK LI SENS/2.048 MHz LB VD RING POWER SUPPLY H RC A TIP D VE I BY E RE F E AL SC , OR T 1 UC B PIN 1 IDENT EN2-TE2(I/O)/SIE D SE/(Mu/A) ON IC MASTER/SLAVE M MOD SELECT SE FRAME 10/20 VSS e B 0.025 M 14 A 0.25 0.10 A1 C IN H M . B M TIP TRANSMIT DATA BUS RECEIVE DATA BUS 2.048 MHz DATA CLOCK 15 TO BACKPLANE C CA S SEATING PLANE B S TO BACKPLANE TIMING AND CONTROL VDD LO1 Vref LO2 LI SDI1 SDI2 MSI/TONE Tx Rx TDC/RDC/XTALout CCI/XTALin UDLT-3 PD MASTER RE1/CLKOUT MODE EN1-TE1 (I/O) SDO1 EN2-TE2(I/O)/SIE SDO2 SDCLK RE2/BCLK LI SENS/2.048 MHz LB VD RING SE/(Mu/A) MASTER/SLAVE MOD SELECT FRAME 10/20 VSS 26 For More Information On This Product, TELECOMMUNICATIONS Go to: www.freescale.com TELECOMMU Freescale Semiconductor, Inc. MC145423 Freescale Semiconductor, Inc... H RC A D VE I BY E RE F E AL SC S O IC EM , OR T UC ND C IN . Digital DNA is a trademark of Motorola, Inc. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals", must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA/EUROPE/Locations Not Listed: Motorola Literature Distribution: P.O. Box 5405, Denver, Colorado 80217. 1-303-675-2140 or 1-800-441-2447 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1 Minami-Azabu. Minato-ku, Tokyo 106-8573 Japan. 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tao Po, N.T., Hong Kong. 852-26668334 TECHNICAL INFORMATION CENTER: 1-800-521-6274 HOME PAGE: http://motorola.com/semiconductors/ For More Information On This Product, Go to: www.freescale.com MC145423/D |
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